This article is a summary and reconstruction of a research report submitted as a hardware architecture assignment during the author's master's studies in computer science. The core arguments remain valid today, and select content has been updated to reflect recent developments in the field.

1. Introduction: The Intelligence Explosion and the Structural Limits of Computing Infrastructure

Starting with GPT-3, AI entered what has been called an era of "intelligence explosion." But beneath this growth, computing infrastructure is showing structural limitations. Data throughput and energy consumption driven by AI demand are rising rapidly, while hardware advancement struggles to keep pace.

The numbers illustrate this imbalance clearly. Global data production is projected to reach 181 zettabytes (ZB) by 2025, and in 2020, data centers worldwide consumed 1.973 trillion kWh of energy — approaching half of the United States' total annual electricity consumption. The cost dimension is equally stark. Training GPT-3 on a single V100 GPU would take 355 years and approximately $4.6 million (based on three-year reserved cloud pricing). While hardware computational performance has tripled every two years, model size has grown 410-fold over the same period.

OpenAI has warned that if this trend continues, the cost of training LLMs by 2027 could approach U.S. GDP. Existing architectures alone cannot close this gap. The transition to "neuromorphic computing" — modeled after the human brain — is no longer a matter of technological choice, but a path that must be seriously pursued.

2. The Twilight of the Von Neumann Architecture: The Memory Wall and the Energy Efficiency Dilemma

The limitations of the Von Neumann Architecture — which has driven computing for decades — are now apparent. Its structure, which stores data and instructions separately and transfers them to a processing unit, has become a structural bottleneck under AI workloads.

The "Memory Wall" is the defining example. Over the past 20 years, maximum hardware computational capacity (FLOPS) increased 60,000-fold, while DRAM bandwidth and interconnect speed grew only 100-fold and 30-fold, respectively. The gap between compute speed and data movement speed has widened continuously over two decades.

Moore's Law — which relies on transistor miniaturization — has also reached its practical limits. Efficiently implementing non-volatile synaptic weights in CMOS-based digital circuits has become increasingly difficult.

In-memory computing — processing computation and storage within the same device to minimize data movement — is the realistic approach to circumventing this structural limitation.

3. The Memristor: The Fourth Fundamental Circuit Element Modeling the Brain's Synapse

The device drawing attention as a way around these structural constraints is the memristor. First predicted mathematically by Leon Chua in 1971 and physically realized at HP Labs in 2008, this device changes resistance according to the amount of charge that has passed through it and retains that state. The fact that its characteristics change based on charge history makes it physically analogous to how synapses in the brain operate.

The basic structure of a memristor is a Metal-Insulator-Metal (MIM) sandwich. The resistance switching (RS) effect — where resistance changes based on electrical stimulation history — divides into three categories by mechanism:

  • ECM (Electrochemical Metallization): Conductive filament formation through metallic cation migration in solid electrolyte
  • TCM (Thermochemical Mechanism): Chemical state changes in oxides driven by temperature increase
  • VCM (Valence Change Mechanism): Oxygen anion migration and lattice valence changes induced by electric fields

Currently, PCM (phase-change materials), CBRAM (Conductive Bridging RAM), ReRAM (oxide-based), and MRAM (magnetic resistance) are competing in this space. These devices store information in multi-level resistance states while simultaneously performing computation. Arranging them in large-scale crossbar arrays forms the computational core of a neuromorphic architecture.

4. Core Mechanisms of Neuromorphic Computation: Hardware Implementation of MVM and STDP

The essence of memristor-based neuromorphic computing lies in implementing complex software algorithms directly through physical laws.

Matrix-Vector Multiplication (MVM) is the most representative example. Ohm's Law and Kirchhoff's Current Law process this operation in hardware instantaneously. The conductance (G) at each crosspoint of the crossbar array represents the matrix weight; the input voltage (V) represents the vector. The resulting current (I) equals the product of the two values according to Ohm's Law (I = G·V), and summing by column yields the matrix product per Kirchhoff's Law. Physical law itself performs the computation — no separate arithmetic unit required.

Memristors also implement STDP (Spike-Timing-Dependent Plasticity), the biological learning principle. The process of strengthening (LTP, Long-Term Potentiation) or weakening (LTD, Long-Term Depression) synaptic connection strength based on the timing difference between pre- and post-synaptic spikes is reproduced directly by the variable resistance characteristics. The hardware itself can learn and adapt without intervention from an external processing unit.

5. Hardware Implementation Case Studies: IBM Neuromorphic Core and HP Neuristor

Theoretical discussion has already moved into the stage of actual hardware implementation.

IBM — Tuma Research Team

IBM's Tuma research team simulated changes in neural membrane potential using PCM-based neurons. The structure maps the process of gradually decreasing resistance according to spike current — leveraging the crystallization dynamics of amorphous phase-change materials — onto the neuron activation state. The key achievement is reproducing "stochastic neural firing," a hallmark of the biological brain, by exploiting device-level randomness.

HP — Pickett Research Team

HP's Pickett research team designed the "Neuristor" using a Mott memristor based on niobium dioxide (NbO2). Grounded in the Hodgkin-Huxley model, this design implements the All-or-Nothing principle — responding only to stimulation above threshold potential — in electronic circuitry. Spike patterns generated by two memristors alternating between SET and RESET reproduced complex brain operations such as signal amplification and periodic firing at the circuit level.

6. Technical Challenges and Breakthrough Strategies: From Sneak Paths to the 3T1C Architecture

Technical problems remain to be solved before commercialization. The "Sneak Path" problem — current leaking into unselected cells in large-scale arrays — is being mitigated using 1T1R (1 Transistor 1 Resistor) or 1S1R (1 Selector 1 Resistor) structures combined with a V/2 biasing scheme.

Device non-idealities such as conductance drift and noise are being addressed through hardware-aware training and mixed-precision in-memory computing approaches.

The 3T1C (3 Transistors 1 Capacitor) circuit structure significantly improves linearity and granularity in weight updates, and is drawing increasing attention as a means of compensating for memristor physical limitations at the architectural level. This structural improvement is expected to contribute to narrowing the accuracy gap in SNNs (Spiking Neural Networks).

7. Conclusion: The Cognitive Computing Future That Memristors Make Possible

Memristor technology is not an extension of semiconductor performance improvement. It is a realistic path toward realizing low-power processing systems that approach the efficiency of the human brain. The industrial implications are substantial. In autonomous vehicles requiring real-time judgment without cloud connectivity, energy-constrained edge computing environments, and IoT applications, neuromorphic systems provide processing efficiency that is difficult to achieve through conventional approaches.

Going forward, competitive advantage in computing will hinge on Co-design capability — the capacity for hardware and algorithms to evolve in tandem by reflecting each other's constraints and strengths. As the Von Neumann architecture approaches its limits, the importance of memristor-based neuromorphic computing will only grow. It stands to become a foundational technology for an era in which AI operates efficiently beyond the walls of the data center.

※ This column is a reconstruction of a hardware architecture research report originally submitted during the author's master's program in computer science.